The present invention relates generally to memory devices and, more particularly, to a voltage regulator circuit for the independent adjustment of pumps in multiple modes of operation of the memory device.
A semiconductor device may be designed for any of a wide variety of applications. Typically, the device includes logic circuitry to receive, manipulate or store input data. The circuitry subsequently generates the same or modified data at an output terminal of the device. Depending on the type of semiconductor device or the circuit in which it is used, the device typically includes circuits which provide internal power signals that are regulated to be substantially independent of fluctuations in the externally generated power input signal(s).
An example of a data storage or memory device having such internal power signal circuits is the DRAM (dynamic random access memory). Conventionally, the DRAM receives an external power signal (Vccx) having a voltage intended to remain constant, for example, at 4.5 volts measured relative to ground. Internal to the DRAM, the power regulation circuit maintains an internal operating voltage signal (Vcc) at a designated level, for example, 2.5 volts. Ideally, Vcc linearly tracks Vccx from zero volts to the internal operating voltage level, at which point Vcc remains constant as Vccx continues to increase in voltage to the designated Vccx level.
DRAMs also typically include a regulated constant pumped supply voltage (Vccp) which is greater than Vcc, for example, four volts. Conventionally, the pumped voltage drives the word lines of a DRAM. The DRAM has memory arrays consisting of a number of intersecting row and column lines of individual transistors or memory cells. The pumped voltage needs to be greater than Vcc to ensure that memory access operations, such as a memory cell reads or writes, are performed both completely and quickly. Ideally, Vccp does not fluctuate. If Vccp is too high, damage to the memory cells may result. If it is too low, the memory chip may have poor data retention or may otherwise operate incorrectly.
The pump used to create the pumped voltage is typically referred to as a Vccp pump. In addition to the Vccp pump, a pump regulator is required and an oscillator may be used to ensure that the pumped voltage Vccp falls within the desired limits described above. The most common oscillator used in the Vccp pump is a standard CMOS (complementary metal oxide semiconductor) ring oscillator. A unique feature of the standard CMOS oscillator is its multi-frequency operation due to its multiplexed circuitry and various oscillator tap points. The oscillator is controlled by a control signal generated by the pump regulator. Whenever the pump regulator issues a pump enable control signal, the oscillator becomes functional and the pump becomes operative.
FIG. 1 illustrates a conventional pump regulator circuit 10. The regulator circuit 10 includes a step down resistance 12, a voltage divider circuit 20, voltage adjustment circuit 40 and a level detect circuit 14. The step down resistance 12 is connected to the pumped voltage Vccp, which is input from a Vccp pump (not shown). The step down resistance 12 is illustrated as a resistor, but it should be appreciated that the resistance 12 could consist of multiple resistors, transistors, diodes, any combinations of these elements or any other circuit element that would cause the pumped voltage Vccp to drop by a specified voltage amount.
The voltage divider circuit 20 is connected between the step down resistance 12 and another voltage (illustrated as a ground potential). The illustrated voltage divider circuit 20 includes a plurality (e.g., five) of series connected n-channel MOSFET (metal oxide semiconductor field-effect transistor) transistors 22, 24, 26, 28, 30. Each transistor 22, 24, 26, 28, 30 has its gate connected to a voltage such as Vcc such that they are always in the active state. In addition, each transistor 22, 24, 26, 28, 30 is typically a long xe2x80x9cLxe2x80x9d device that causes a relatively small current draw when activated (i.e., it is well known in the art that the amount of current a MOSFET can carry is proportional to W/L, where W is the width of the transistor and L is its gate length). Thus, if there were no other elements in the circuit 10, the resistance 12 and the voltage divider circuit 20 would divide the pumped voltage Vccp in accordance with their resistances and cause a predetermined reference voltage Vref to appear at node A. It should be noted that the voltage divider circuit 20 may comprise other elements besides the illustrated transistors 22, 24, 26, 28, 30 and it should be appreciated that the circuit 20 could consist of multiple resistors, transistors, diodes, any combinations of these elements or any other circuit element that would create resistance effecting the voltage in a desired manner.
The reference voltage Vref is input into the level detect circuit 14. The circuit 14 can be any conventional circuit and thus, the internal circuitry of the level detect circuit 14 is not shown for convenience purposes. As is known in the art, in operation the typical level detect circuit 14 inputs the reference voltage Vref (sometimes referred to as a normalized voltage) and compares it to a threshold voltage, which when exceeded, provides a signal to turn off the pump. Similarly, if the reference voltage Vref is less than the threshold, the circuit 14 provides a signal that turns on the pump. This is typically done by feeding the reference voltage into a modified inverter stage having an adjustable trip point. The trip point is modified with feedback to provide hysteresis for the circuit 14. Subsequent inverter stages provide additional gain and boost the reference voltage signal to the full CMOS level necessary to enable or disable the oscillator. Minimum and maximum operating voltages for the Vccp pump are controlled by the first inverter stage trip point, hysteresis and diode connected transistors voltages.
The output of the level detect circuit 14 is a pump on/off signal. The pump on/off signal is used as a control signal for the oscillator (not shown) connected to the Vccp pump. Whenever the pump on/off signal is set to a value indicating that the Vccp pump should be enabled, the oscillator becomes functional and enables the pump.
There is a need for the regulator circuit 10 to operate based on different operating voltages (e.g., Vcc) and pumped voltages (e.g., Vccp). The different voltages may be required, for example, because a particular system has a manufacturing specification mandating specific operating and pumped voltages. Accordingly, the regulator circuit 10 typically includes the adjustment circuit 40 to adjust the voltage divider circuit 20 so that the proper pump on/off signal PUMP ON/OFF can be generated regardless of the Vcc and Vccp voltage levels.
The adjustment circuit 40 includes a plurality (e.g., five) of n-channel MOSFET transistors 42, 44, 46, 48, 50. Each transistor 42, 44, 46, 48, 50 has their source and drain terminal connected across the source and drain terminal of a respective voltage divider transistor 22, 24, 26, 28, 30. Unlike the gate terminals of the voltage divider transistor 22, 24, 26, 28, 30, the gate terminals of the adjustment transistors 42, 44, 46, 48, 50 do not have to be connected such that they are always in the active state. Instead, the gate of each adjustment transistor 42, 44, 46,48, 50 can be connected such that the transistor 42, 44, 46, 48, 50 is active or inactive.
For example, in FIG. 1, the fourth and fifth adjustment transistors 48, 50 are connected to a voltage such as Vcc, which activates both transistors 48, 50. With both of these adjustment transistors 48, 50 in the active state, their corresponding voltage divider transistors 28, 30 are shunted. This, removes the resistances associated with the fourth and fifth voltage divider transistors 28, 30, which changes the voltage divider circuit 20 and alters the voltage level of the reference voltage Vref. Thus, the adjustment transistors 48, 50 act as switches that can switch in or out (i.e., do not shunt or shunt) the resistance associated with their corresponding voltage divider transistors 28, 30.
As noted above, the other adjustment transistors 42, 44, 46 do not have to connected such that they are always in the active state either. For example, the first three adjustment transistors 42, 44, 46 are connected to two signal lines OPT1, OPT2. The signal lines OPT1, OPT2 can be set by test keys, fuses or any other manner such that their respective adjustment transistors 42, 44, 46 are active or inactive. If any of these adjustment transistors 42, 44, 46 are set to the active state, then their corresponding divider transistor 22, 24, 26 will be shunted. Likewise, if any of the first three adjustment transistors 42, 44, 46 are set to the inactive state, then their corresponding divider transistor 22, 24, 26 will not be shunted. Thus, for the illustrated regulator circuit 10, depending on how the signal lines OPT1, OPT2 are set, the voltage divider circuit 20 may include none, all three or some of the first three divider transistors 22, 24, 26 (i.e., in FIG. 1 the fourth and fifth divider transistors 28, 30 have already been shunted and thus, only the first three divider transistors 22, 24, 26 can add resistance to the divider circuit 20).
Thus, depending upon the manufacturing specifications of the memory circuit utilizing the pumped voltage Vccp and the regulator circuit 10, the adjustment circuit 40 can be configured such that the voltage divider circuit 20 generates the proper reference voltage Vref Typically, the regulator circuit 10 controls the oscillator such that it is operated at a higher frequency when the DRAM is in a power-up operating mode than in nominal operation because this will assist the Vccp pump in initially charging DRAM components such as load capacitors. There is a third operating mode that often requires the regulator circuit 10 to operate the oscillator/pump in a different manner. This third mode known as the burn-in mode, which is a test mode, often times requires a much different pumped voltage Vccp than the one used during nominal operation. To compensate for this, the regulator circuit 10 often contains a burn-in transistor 60. The burn-in transistor 60 has its source and drain connected across the source and drain of one of the voltage divider transistors 26. The gate of the burn-in transistor 60 is connected to a burn-in signal line BURNIN. When the memory circuit utilizing the regulator circuit 10 undergoes a burn-in test, the burn-in signal line BURNIN is activated, which activates the burn-in transistor 60. Once activated, the burn-in transistor 60 shunts its corresponding voltage divider transistor 26, which alters the voltage divider circuit 20 and the reference voltage Vref.
As can be seen from FIG. 1, the prior art regulator circuit 10 can only shunt one divider transistor 26 during burn-in mode. If a vastly different pumped voltage Vccp is required for the burn-in test, then the voltage divider and adjustment circuits 20, 40 would require some modifications. This solution is unacceptable because this changes the design of the circuit 10 for nominal operation, which has been designed, tested and qualified as meeting nominal operating mode specifications. Once the design is changed, the part would have to be re-tested and re-qualified for all modes of operation. Moreover, the only way to change the design of the circuitry 10 would be to re-mask and re-fabricate it. This would be rather costly with respect to time and money.
Accordingly, there is a desire and need for a regulator circuit that can adjust the operation of the Vccp pump for different independent modes of operation (e.g., nominal and burn-in modes) that would not require re-designing, re-masking or the re-fabrication of its circuitry.
Furthermore, manufacturing process variations may render the capability of the burin-in transistor 60, adjustment circuit 40 and voltage divider circuit 20 ineffective for their intended purposes, which could adversely impact the pumped voltage Vccp. Process variations could render one lot of memory circuits different from another lot of memory circuits even though they utilize the same mask, design, etc. This could lead to unexpected variations of the pumped voltage Vccp. As noted earlier, if Vccp is too high, damage to the memory cells, and higher current may result, if it is too low, the memory chip may have poor data retention or may otherwise operate incorrectly.
Accordingly, there is a desire and need for a regulator circuit that can adjust the operation of the Vccp pump for different modes of operation that can compensate for process variations.
The present invention provides a regulator circuit that can adjust the operation of a voltage pump for different independent modes of operation without re-designing, re-masking or re-fabricating its circuitry.
The present invention also provides a regulator circuit that can adjust the operation of the voltage pump for different modes of operation that can compensate for process variations.
The above and other features and advantages are achieved by providing a regulator circuit with at least two independently selectable and adjustable adjustment circuits. Each adjustment circuit is adapted to be connected across a standard voltage divider circuit used to create a reference voltage for operating a voltage pump. Between each adjustment circuit and the voltage divider circuit is an associated connection circuit. Each connection circuit is controlled by an associated control signal. When activated by its respective control signal, the connection circuit connects its associated adjustment circuit to the voltage divider circuit so that the reference voltage is generated by the voltage divider circuit as adjusted by the connected adjustment circuit. Since the amount of adjustment each adjustment circuit can introduce is also independently selectable, the regulator circuit can adjust the operation of the voltage pump for different modes of operation that can compensate for process variations without the need to re-design, re-mask or re-fabricate the circuitry.